The effort to design and build chips containing a large number of circuits has resulted in miniaturization of the devices both horizontally and vertically. This miniaturization or shrinking has imposed new requirements on processes and materials used in contacts and interconnections. For example, in field effect transistor (FET) devices, the gate lengths and the depth of source and drain diffusion regions are continually being scaled down in order to achieve faster device speed and build more devices on unit area of the silicon chip. Already, the gate lengths are in the sub-micron range and the diffusion regions are in the 0.1 micron range. Hence, it has become important that the process and material used to make the contact and interconnect to the diffusion region must not react therewith and cause no degradation of the diffusion region characteristics. To achieve wiring of many possible circuits, a preferred approach has been to use a wiring level specifically to connect devices close to each other. Such closely located devices are connected together by short conductive straps, and appropriately this wiring is called local interconnection. It is important that the local interconnection contacting the device opening makes good electrical contact to the device and at the same time is reliable. Similar to FETs, dimensions in bipolar devices have also been miniaturized. The vertical dimension of the base width is less than 1000 A while the contact opening is in the sub micron range. In the case of advanced bipolar devices, direct contact to device regions are avoided by use of polysilicon layers on emitter and extrinsic base contacts. This reduces the concern of reactivity. However, low electrical contact resistance is still required between the polysilicon and the local interconnection material.
Yet another requirement for high density circuits is the capability of using a "partially covered" contact design, wherein an interconnection strap covers the contact opening only partially. The achievement of good electrical contact becomes more challenging when partially covered contacts are allowed, because of the decrease in intersecting area between the contact and the strap. A typical "partially covered" contact design is illustrated in FIG. 1. Referring to FIG. 1, the contact opening 10 is larger than the width of the interconnection strap 20. The strap 20 can intersect 10 in ways other than shown, but in all cases, the area of the contact opening will not be fully covered by the strap 20. The benefit of using a partially covered contact is the ability to use the smallest allowed features for lines and spaces, thereby realizing the wiring of a larger number of devices by permitting high density wiring.
Usually, the local interconnection is made over a non-planar surface, which means significant overetching of the interconnect material will be required to clear unwanted material from everywhere except under the resist mask. Of important concern, is the thickness variation of the film resulting from the device topography, which can result in incompletely etched residues. The residues can cause electrical shorts between adjacent contacts or interconnects and result in yield losses.
The key requirements for the local interconnect process and material can be summarized as follows: ability to use partially covered contact design, ability to overetch, good electrical contact to silicon and no reaction with the device contact region.
The present art of local interconnection attempts to achieve the above objectives, but is usually deficient in meeting some of the goals. This will be shown with the discussion of the following prior art. FIG. 2 shows a cross section of an FET device and a resulting interconnect structure disclosed by Hayashida et al. (IEEE VMIC Conference Proceedings, June, 1991, p. 332). The Hayashida et al. article discloses a silicon substrate 25 including an FET device, with a source 55 and drain 56 regions (N+), and a gate structure 45 formed by known processes not discussed here. After the contact apertures 46, 46' are opened, corresponding to the source and drain regions, a thin silicon oxide 50, also referred to as a "barrier oxide", is grown over the exposed silicon surfaces at the contact openings. FIG. 2 further shows the FET device with recessed oxide device isolation 35. A polysilicon interconnect film is blanket deposited and etched to make wiring 30 by use of a resist pattern (not shown) and by use of the barrier oxide layer 50 underneath as an etch stop. Subsequently the barrier oxide is removed from the contact region except under the polysilicon by a different etching process, leaving the oxide 50' underneath a polysilicon strap 30 and the contact opening surface 46 as shown. The silicon oxide layer 50, electrically insulates the polysilicon strap 30 from the contact. The polysilicon only partially covers the contact opening area to the source or drain. At this point, Hayashida et al., deposits a layer of blanket Titanium 40 over all surfaces. By suitable heating, the Titanium film reacts with the silicon over the contact surface and with the polysilicon top surface and sidewalls to form Titanium silicide. Unreacted titanium is later removed from the device surface. However, there is no silicide formation with the sidewall of the barrier oxide 50'. The Titanium silicide link over the side wall of oxide 50' primarily occurs from the overgrowth of the silicide from the polysilicon 30 sidewall and that from silicon contact surface 46 adjacent to the oxide film 50'. This Titanium silicide link going over the sidewall of the silicon oxide 50', is a vulnerable part of the bridging between the polysilicon strap and the silicon contact. In addition the requirement of the strap material not reacting with the doped silicon at the contact is not achieved. Lee et al. (IEDM, 1988 proceedings pp. 450-453) uses a slightly different process than that of Hayashida. The process steps are identical until the polysilicon is etched over the contact using the field oxide as the etch stop. At this point, in the Lee et al. process, the field oxide is etched away, and tungsten is deposited selectively over the silicon in the contact and the polysilicon strap, the selective W layer forming the electrical bridge over the field oxide step. Since W does not nucleate on the sidewall of the thin oxide, the film bridging comes from the overgrowth of the grains nucleating on the polysilicon sidewall and the contact silicon surface. The integrity of the W film to provide a reliable bridge is a main concern with this approach. In both these processes, a main draw back is that the area of the device contact under the polysilicon is unused, thereby potentially causing high contact resistance. Further, this area reduction is likely to vary depending on lithography and process tolerances. In a worst case, the area reduction penalty can become unacceptable for small contacts. In a third method (Tang et al, IEDM p. 590, 1985), the contact regions are silicided and a titanium nitride film is etched to form the local interconnect, by use of titanium silicide as an etch stop layer. The main drawback of this approach is the need to silicide the contact, which is not desirable for shallow diffusions. It is clear that all these methods have significant drawbacks and do not meet the objectives described earlier. It would be particularly valuable in the art, especially as it relates to local interconnection on a semiconductor substrate, to provide a method that allows partially overlapping contact, allows overetching for yield on devices with topography, makes a good electrical contact (low resistance) to silicon and does not degrade the device contact by reacting with the silicon at the contact. The concern with device degradation is serious when the diffusion depths are shallow (about 0.1 micron), as the case with many future devices.